Particular embodiments generally relate to adaptive voltage scaling.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Adaptive voltage scaling may be used on system-on-a-chip (SOC) designs to save dynamic power and leakage power. Process, power supply voltage level, and temperature (PVT) corners cause variation in timing for paths of an integrated circuit (IC) chip. For example, the delay for a NAND gate in a worst case scenario (e.g., slowest PVT corner) may be several times more than that in a best case scenario (e.g., fastest PVT corner). Conventionally, the SOC designs use the slowest PVT corner to target all timing corners, which is not efficient in power saving.
Adaptive voltage scaling may be used to improve the power consumption on the IC. Adaptive voltage scaling is used to apply a minimum power supply voltage that is required to meet critical path timing in a PVT corner for the chip. For example, a system runs at 500 MHz with a timing budget for a critical path of two nanoseconds (ns). Depending on the real delay timing measured for the critical path, the power supply voltage is adjusted to meet the timing requirements. For example, if the real critical path timing delay is 1.2 ns, it is determined that the real critical path timing delay is unnecessarily fast. In this case, the power supply voltage may be lowered to increase the real critical path timing delay. Lowering the power supply voltage increases the delay to bring the real critical path timing closer to the desired timing budget. Also, by lowering the voltage, power is saved. In another example, if the real critical path delay is 2.1 ns, then the power supply voltage can be increased to decrease the real critical path delay to bring the delay closer to the desired timing budget. Adaptive voltage scaling continuously measures the real critical path delay and attempts to make the critical path delay to be 2.0 ns to maximize power saving.
Measuring the delay requires a special circuit on the chip for performing the adaptive voltage scaling, which uses area on the chip and increases cost. For example, the adaptive voltage scaling circuit may determine when to increase or decrease the voltage based on a frequency of a reference signal and temperature measured from the chip. Accordingly, special circuits that can measure the frequency and the temperature are needed. Additionally, logic to interpret the measured frequency and temperature, and determine whether to increase or decrease the power supply voltage is also needed. This increases the cost and also requires a hardware change to incorporate the frequency and temperature measuring circuits.